Methods of minimizing power consumption in CMOS VLSI design

  • A. I. Belous Belarusian State University of Informatics and Radioelectronics, Minsk, Belarus
  • I. A. Murashko Scientific and Technical Center "Belmicrosystems" of Scientific and Production Association "Integral", Minsk, Belarus
  • V. S. Syakersky Scientific and Technical Center "Belmicrosystems" of Scientific and Production Association "Integral", Minsk, Belarus
Keywords: micropower devices, dissipation power, static dissipation power, dynamic dissipation power, CMOS inverter

Abstract

The main methods that allow reducing the amount of dissipated power at the stages of CMOS VLSI design are presented. A classification of power dissipation sources is provided. Several practical measures for reducing energy losses and increasing the performance of CMOS microprocessors are discussed.

Published
2008-04-30
How to Cite
Belous, A. I., Murashko, I. A., & Syakersky, V. S. (2008). Methods of minimizing power consumption in CMOS VLSI design. Technology and Design in Electronic Equipment, (2), 39-44. Retrieved from https://tkea.com.ua/index.php/journal/article/view/TKEA2008.2.39
Issue
No. 2 (2008): Tekhnologiya i konstruirovanie v elektronnoi apparature
Section
Articles

Copyright (c) 2008 Belous A. I., Murashko I. A., Syakersky V. S.

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.