Instrumental and technological modeling of autoemission silicon microcathodes

Abstract

A structure of a system for converting topological information for digital lithography is proposed. A method for forming local three-dimensional SOI (Silicon-on-Insulator) structures has been developed, which makes it possible to create both planar and three-dimensional device elements and contacts. On the SOI structures, a control high-voltage MOS transistor and a memory cell with a signal shaper for storing topological information have been designed. Expert optimization of the memory cell topology has made it possible to significantly reduce its area compared to that of a cell fabricated using standard n-channel MOS technology.